According to the Sheeva Bom the NAnd flash chips are (or can be) Samsung K9F4G08U0A-PCB0, although I have seen people showing Hynix ICs on this forum!
Looking at the K9F4G08U0A-PCB0 data sheets, reveals the following gems:-
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is
presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.
* : Each K9F4G08U0A chip in the K9K8G08U1A has Maximun 80 invalid blocks.
Parameter Symbol Min Typ. Max Unit
K9F4G08U0A NVB 4,016 - 4,096 Blocks
K9K8G08U1A NVB 8,032* - 8,192* Blocks
NAND Flash Technical Notes
Identifying Initial Invalid Block(s)
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)
have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)
does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor.
The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on
00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial
invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in
most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the
initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following
suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.
The interesting statistic is that there can be up to 80 invalid blocks in each chip allowable as a "good" part by Samsung.
The first block is guaranteed to be good for 1000 program/erase cycles.
Here is the general spec:-
• Voltage Supply
- 2.70V ~ 3.60V
- Memory Cell Array : (512M + 16M) x 8bit
- Data Register : (2K + 64) x 8bit
• Automatic Program and Erase
- Page Program : (2K + 64)Byte
- Block Erase : (128K + 4K)Byte
• Page Read Operation
- Page Size : (2K + 64)Byte
- Random Read : 25μs(Max.)
- Serial Access : 25ns(Min.)
512M x 8 Bit / 1G x 8 Bit NAND Flash Memory
• Fast Write Cycle Time
- Page Program time : 200μs(Typ.)
- Block Erase Time : 1.5ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
-Endurance : 100K Program/Erase Cycles(with 1bit/512Byte
- Data Retention : 10 Years
• Command Driven Operation
• Intelligent Copy-Back with internal 1bit/528Byte EDC
• Unique ID for Copyright Protection
• Package :
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
52 - Pin ULGA (12 x 17 / 1.00 mm pitch)
52 - Pin ULGA (12 x 17 / 1.00 mm pitch)
You can see the endurance, (life) is -Endurance : 100K Program/Erase Cycles(with 1bit/512Byte
You can get your own copy of the data sheet from many web sites (alldatasheets is a good one)
There is also interesting reads about NAND flash on the MTD website.
The MTD website www.linux-mtd.infradead.org
does say that NAND flash CRITICAL of interrupts to its operating cycle.
Sudden unexpected power fails or shutdowns may appear as bad block errors
AFAICS The whole NAND flash page has to be written in one go from a buffer elsewhere in the system, if the power fails ungracefully half way through writing the page then the page is left with a CRC error.
Which may explain the problems some people are seeing