I thought the Marvell processor only brought out 30 bits of address space, so unless you are talking externally segmenting the memory, 1G is the limit.
Where do you see that there are 30 bits of address space? According to section 4 of the 88F6281 functional spec (http://www.marvell.com/files/products/embedded_processors/kirkwood/FS_88F6180_9x_6281_OpenSource.pdf
The device integrates an DDR SDRAM (Double Data Rate-Synchronous DRAM) controller that supports up to four DRAM banks (four DRAM chip selects). It incorporates an 18-bit address bus (M_A[14:0] and M_BA[2:0]) and a 16-bit data bus (M_DQ[15:0]).
The device supports 256 Mb, 512 Mb, 1 Gb, and 2 Gb DDR2 SDRAM devices, with up to 2 GB total address space.
I want to know what parts are suitable to achieve a design with 2 GB of RAM.